A variety of memory devices are presently available with varying characteristics. Dynamic Random Access Memory (DRAM) has the advantage that the number of gates per cell is small and the density is generally quite high. On the other hand, DRAM is disadvantageously prone to data loss if the individual rows of data are not periodically refreshed. Accordingly, known systems have used external or internal refresh circuitry to prevent data loss. External circuitry complicates the design of an external memory controller and may therefore be disadvantageous. DRAMs disadvantageously have relatively long array cycle times as compared to other memory devices (e.g., static memories) and therefore may act as a bottleneck for a processor that requests memory more quickly than the DRAM can provide it.
As an alternative, Static Random Access Memory (SRAM) devices utilize a greater number of transistors per memory cell and, as a result, do not require refreshing. Moreover, the transistor interconnections allow data to be read from and written to the device significantly more quickly than DRAMs. Unfortunately, the cost of SRAMs per bit is significantly more expensive than the cost of DRAMs per bit. Accordingly, it is often prohibitively expensive to use SRAM for a computer's main memory, and instead a small amount of SRAM is used only for a memory cache between the processor and a larger amount of DRAM.
As an alternative to both DRAM and SRAM designs, hybrid memories have been introduced that have some of the characteristics of both DRAM devices and SRAM devices. One such device is known as an “Enhanced DRAM” (EDRAM) and is described in U.S. Pat. Nos. 5,887,272, 5,721,862, and 5,699,317 (hereinafter “the '272 patent,” “the '862 patent”, and “the '317 patent,” respectively), each naming Sartore et al. as inventors. (Those inventions have been assigned to the parent company of the assignee of the present invention.) The EDRAM devices disclosed therein provide increased data throughput by providing at least one row register (i.e., a read cache) associated with each DRAM sub-array or with each group of DRAM sub-arrays. Although an EDRAM device can achieve the higher data rate, resembling SRAM access speed, for accesses to data stored in the row register, an EDRAM device still requires externally initiated refresh operations. Column 15, lines 42-56, of the '272 patent discloses that an external signal labeled “/F” controls a refresh cycle. This characteristic requires the use of a memory controller that understands the operation of EDRAM devices and, thus, disadvantageously includes the additional circuitry for initiating those refresh cycles.